The area occupied by an integrated circuit device is desired to be minimized for being used in smaller portable electronic devices. Accordingly, a three dimensional stacked memory device is formed in the prior art for minimizing the area occupied by the memory device.
For example, U.S. Pat. No. 6,133,640 to Leedy discloses a memory device with multiple memory cell arrays stacked on top of a memory controller. However, Leedy just discloses one three dimensional memory device and not a three dimensional memory module/system.
U.S. Pat. No. 6,768,163 to Tanaka et al. discloses a first semiconductor substrate with a memory cell array stacked on a second semiconductor substrate having a word line control circuit to control the word lines of the memory cell array. Tanaka also discloses one three dimensional memory device and not a three dimensional memory module/system.
In addition, Tanaka discloses the integrated circuit package with the stacked semiconductor substrates having vertical terminals disposed on the outside periphery of the substrates. Such vertical terminals disposed on the outside periphery of the substrates disadvantageously increase the area occupied the three dimensional memory device of Tanaka.
U.S. Pat. No. 7,123,497 to Matsui et al. discloses multiple DRAM (dynamic random access memory) chips stacked on top of an IO (input output) chip. TSVs (through semiconductor vias) are formed through such chips for interconnection among such chips. TSVs are vertical electrical connections formed to pass completely though the semiconductor substrate of the stacked chips. However, Matsui is directed to using the IO chip only for conversion of data width and transfer rate during transfer of data to/from the DRAM chips.